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VHDL input sample.vhd

entity counter is
  port (
    clk   : in  std_logic;
    rst_n : in  std_logic;
    q     : out unsigned(7 downto 0)
  );
end entity;

architecture rtl of counter is
begin
  p_count: process(clk, rst_n)
  begin
    if rst_n = '0' then
      q <= (others => '0');
    elsif rising_edge(clk) then
      q <= q + 1;
    end if;
  end process;
end architecture;

SystemVerilog output server result

module counter (
  input  logic       clk,
  input  logic       rst_n,
  output logic [7:0] q
);

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      q <= 8'd0;
    end else begin
      q <= q + 8'd1;
    end
  end

endmodule