vhdl2sv Commercial VHDL to SystemVerilog translation

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Support Policy

Support channels, scope, reasonable-efforts model, and bug-report guidance.

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Last updated: 2026-04-13

This Support Policy describes the baseline support approach currently intended for vhdl2sv.

1. Support contact

Support contact: support@vhdl2sv.com

Customers reporting bugs or suspected mistranslations should include enough material for reproduction, which may include:

  • the affected VHDL source or a minimized reproducer
  • the generated SystemVerilog output
  • the vhdl2sv version/build stamp
  • a description of the observed incorrect behavior
  • simulator or compiler logs, if relevant

2. Scope of support

Baseline support currently focuses on:

  • reproducible translator crashes
  • reproducible parser/analyzer/emitter bugs
  • clear mistranslations
  • licensing/activation issues
  • installer or desktop application problems

Support does not automatically include:

  • custom feature development
  • project-specific consulting
  • review of large proprietary codebases without a specific bug report
  • guaranteed response or resolution times unless separately agreed

3. Channels

Support is currently provided primarily by email.

4. Response model

Support is provided on a reasonable-efforts basis unless a separate written support commitment is agreed.

5. Confidentiality

Customers should avoid sending more source code than necessary for reproduction. If a customer needs confidential handling terms beyond the baseline legal documents, that should be agreed separately.